Semiconductor component manufacturers are constantly improving the performance of their components while lowering their cost of manufacture. One way manufacturers have reduced costs has been to increase the device density on a single semiconductor wafer by shrinking the device sizes. Although this increases the number of semiconductor components that can be manufactured from a single semiconductor wafer, it also increases the complexity of the manufacturing processes. For example, the metallization systems used in small geometry semiconductor devices comprise contact openings having high aspect ratios, i.e., the ratio of the height of the contact opening to its width. The contact openings are typically lined with a barrier material prior to being filled with a metal such as tungsten or copper. A drawback of these high aspect ratio contact openings is the difficulty in lining the sidewalls near the bottoms of the contact openings. Because the contact openings are not completely lined with a barrier material, the metal filling them may contact the dielectric material from which the contact openings are made. When the metal is tungsten deposited using tungsten hexafluoride as a precursor, the tungsten hexafluoride corrodes the dielectric material. On the other hand, when the metal is copper, copper atoms are capable of diffusing into the semiconductor device thereby contaminating the semiconductor device and causing it to fail. Another drawback of metallization systems having high aspect ratio contact openings is that they require aggressive Chemical Mechanical Polishing (CMP) techniques in which the CMP slurry comprises a highly reactive component in combination with large abrasive materials. The abrasive materials lodge in the contact openings causing the formation of voids during the metal deposition step. The voids increase the resistance of the metallization system and, if large enough, can create electrical opens in the metallization systems, which in turn result in electrical failure of the semiconductor components.
Accordingly, what is needed is a semiconductor component having high aspect ratio contact openings with sufficient liner coverage to preclude device contamination and a method for manufacturing the semiconductor component that mitigates void formation.